网址:https://hdlbits.01xz.net/wiki/Exams/m2014_q4k
自己写:
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg r_in1;
reg r_in2;
reg r_in3;
always@(posedge clk)begin
if(resetn == 1'b0)
begin
r_in1 <= 1'b0;
r_in2 <= 1'b0;
r_in3 <= 1'b0;
end
else
begin
r_in1 <= in;
r_in2 <= r_in1;
r_in3 <= r_in2;
out <= r_in3;
end
end
endmodule
第二种方法:
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg [3:1] q;
always @ (posedge clk)
begin
if (~resetn)
{q,out} <= 4'b0;
else
begin
q[3] <= in;
q[2] <= q[3];
q[1] <= q[2];
out <= q[1];
//{q,out} <= {in, q};
end
end
endmodule